In some cases, transistors can be formed from a semiconductor substrate that has a fin feature extending from a surface of the semiconductor substrate. The fin feature can extend substantially perpendicular to a planar surface of the semiconductor substrate. The fin feature can also have a thickness that is less than the thickness of the semiconductor substrate. Thus, by extending from a surface of the semiconductor substrate and having a thickness less than a thickness of the semiconductor substrate, the fin feature may resemble a “fin” extending above the surface of the semiconductor substrate. Respective gates of the transistors can be formed by disposing a material, such as a polycrystalline silicon (also referred to herein as “polysilicon”), on multiple surfaces of the fin feature. For example, the gates of the transistors can be formed by encasing a portion of the fin in polysilicon. Additionally, the source regions and the drain regions of the transistors can be formed from doped regions of the fin feature. In particular embodiments, gates of multiple transistors can be formed around a single fin feature. In these scenarios, the transistors can be electrically isolated to decrease interference between the transistors and minimize delays that may occur when the transistors change states.
In some cases, transistors formed from semiconductor substrates having fin features have been isolated using a number of techniques. In one example, the transistors have been isolated by placing an isolation gate between the transistors. In this example, the isolation gates include electrical features that are coupled to a supply voltage and/or a drain voltage. The connection of the isolation gates to electrical features of an integrated circuit can result in a parasitic capacitance that causes a delay in the response of the transistors to a state change. Further, the area covered by the isolation gates can be relatively large.
In another example, transistors formed from substrates having fin features can be isolated by performing a fin cut to cut through the fin feature between the transistors. The size of the fin cut is often limited because of lithographic techniques and has a width that is 30 nm or greater, which decreases the density of transistors formed on the substrate. Furthermore, the fin cut can remove contact between the polysilicon and the fin, which can inhibit the process for embedding stressors in the semiconductor substrate, such as SiGe and/or SiC, which are used to increase the performance of the transistors.
In still another example, regions of polysilicon can be placed at the ends of transistors after the fin cut is performed to create a polysilicon connection with the fins in order to facilitate the processes used to embed the stressors into the substrate. However, the regions formed using this technique have widths limited by 2-D lithography resolution (for example, at least 74 nm in some FinFET technologies), which reduces the density of transistors formed on the substrate.